AD9887A Datasheet, PDF (1/44 Pages) Analog Devices – Dual Interface for Flat Panel Displays

Dual Interface for
Flat Panel Displays
AD9887A
FEATURES
Analog Interface
170 MSPS Maximum Conversion Rate
Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 170 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamping
4:2:2 Output Format Mode
Digital Interface
DVI 1.0 Compatible Interface
170 MHz Operation (2 Pixel/Clock Mode)
High Skew Tolerance of 1 Full Input Clock
Sync Detect for “Hot Plugging”
Supports High Bandwidth Digital Content Protection
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Micro Displays
Digital TVs
GENERAL DESCRIPTION
The AD9887A offers designers the flexibility of an analog interface
and digital visual interface (DVI) receiver integrated on a single
chip. Also included is support for High Bandwidth Digital Content
Protection (HDCP). The AD9887A is software and pin-to-pin
compatible with the AD9887.
Analog Interface
The AD9887A is a complete 8-bit 170 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 170 MSPS encode
rate capability and full-power analog bandwidth of 330 MHz
supports resolutions up to UXGA (1600 × 1200 at 60 Hz).
The analog interface includes a 170 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), and pro-
grammable gain, offset, and clamp control. The user provides
only a 3.3 V power supply, analog input, and HSYNC. Three-
state CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9887A’s on-chip PLL generates a pixel clock from
HSYNC. Pixel clock output frequencies range from 12 MHz to
170 MHz. PLL clock jitter is typically 500 ps p-p at 170 MSPS.
The AD9887A also offers full sync processing for composite
sync and sync-on-green (SOG) applications.
REV. 0
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FUNCTIONAL BLOCK DIAGRAM
REFIN
R_AIN
G_AIN
B_AIN
HSYNC
VSYNC
COAST
CLAMP
CKINV
CKEXT
FILT
SOGIN
SCL
SDA
A₁
A₀
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
R_TERM
DDCSCL
DDCSDA
MCL
MDA
ANALOG INTERFACE
CLAMP
A/D
CLAMP
A/D
CLAMP
A/D
REF
8
8
8
8
8
8
8
8
8
2
SYNC
PROCESSING
AND CLOCK
GENERATION
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
8
8
8
8
8
8
DVI
RECEIVER
8
8
8
2
R_OUTA
R_OUTB
G_OUTA
G_OUTB
B_OUTA
B_OUTB
DATACK
HSOUT
VSOUT
SOGOUT
8
S_CDT
8
8
R_OUTA
R_OUTB
G_OUTA
G_OUTB
M8
U
X
8
E
S
8
2
B_OUTA
B_OUTB
DATACK
DE
HSOUT
VSOUT
HDCP
AD9887A
REFOUT
R_OUTA
R_OUTB
G_OUTA
G_OUTB
B_OUTA
B_OUTB
DATACK
HSOUT
VSOUT
SOGOUT
DE
Digital Interface
The AD9887A contains a DVI 1.0 compatible receiver and
supports display resolutions up to UXGA (1600 Ï« 1200 at 60 Hz).
The receiver operates with true color (24-bit) panels in 1 or
2 pixel(s)/clock mode and features an intrapair skew tolerance
of up to one full clock cycle.
With the inclusion of HDCP, displays may now receive encrypted
video content. The AD9887A allows for authentication of a
video receiver, decryption of encoded data at the receiver, and
renewability of that authentication during transmission as specified
by the HDCP v1.0 protocol.
Fabricated in an advanced CMOS process, the AD9887A is
provided in a 160-lead MQFP surface-mount plastic package
and is specified over the 0°C to 70°C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.