AD9777BSVZ Datasheet, PDF (1/60 Pages) Analog Devices – 16-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+ D/A Converter

16-Bit, 160 MSPS 2x/4x/8x
Interpolating Dual TxDAC+^® D/A Converter
AD9777
FEATURES
16-bit resolution, 160 MSPS/400 MSPS input/output
data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Excellent ac performance
SFDR −73 dBc @ 2 MHz to 35 MHz
WCDMA ACPR 71 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or
TTL/CMOS/LVPECL compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: typical 1.2 W @ 3.3 V
On-chip 1.2 V reference
80-lead thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
FUNCTIONAL BLOCK DIAGRAM
AD9777
16
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
16
DATA
ASSEMBLER
HALF-
BAND
FILTER1*
I
16
16
LATCH
HALF- HALF-
BAND
BAND
FILTER2* FILTER3*
16
16
Q
16
16
LATCH
16
16
COS
SIN
f_DAC/2, 4, 8
SIN
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
WRITE
SELECT
MUX
CONTROL
/2
CLOCK OUT
/2
/2
SPI INTERFACE AND
CONTROL REGISTERS
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
FILTER
BYPASS
MUX
/2
COS
(f_DAC)
PRESCALER
PHASE DETECTOR
AND VCO
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
IDAC
GAIN
DAC
OFFSET
DAC
I/Q DAC
GAIN/OFFSET
REGISTERS
IDAC
I_OUT
DIFFERENTIAL
CLK
Rev. C
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