AD6622 Datasheet, PDF (1/28 Pages) Analog Devices – Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP

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FEATURES
Wideband Digital IF Parallel Output
Wideband Digital IF Parallel Input
Allows Cascade of Chips for Additional Channels
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
High-Speed CIC Interpolating Filter
NCO Frequency Translation
Worst Spur Better than 100 dBc
Tuning Resolution Better than 0.02 Hz
Real or Complex Outputs
Digital Summation of Channels
Clipped or Wrapped Overrange
Two’s Complement or Offset Binary Output
Separate 3-Wire Serial Data Input for Each Channel
Microprocessor Control
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
WBCDMA
Wireless Local Loop Base Stations
Phase Array Beam Forming Antennas
Four-Channel, 75 MSPS Digital
Transmit Signal Processor (TSP)
AD6622
FUNCTIONAL BLOCK DIAGRAM
CH A SPORT
RCF
CIC
FILTER
NCO
18
CH B SPORT
RCF
CIC
FILTER
NCO
CH C SPORT
RCF
CIC
FILTER
NCO
18
CH D _SPORT
RCF
CIC
FILTER
NCO
JTAG
␮PORT
PRODUCT DESCRIPTION
The AD6622 comprises four identical digital Transmit Signal
Processors (TSPs) complete with synchronization circuitry and
cascadable wideband channel summation. An external digital-
to-analog converter (DAC) is all that is required to complete a
wide band digital up-converter. On-chip tuners allow the relative
phase and frequency for each RF carrier to be independently
controlled.
Each TSP has three cascaded signal processing elements: a
RAM-programmable Coefficient interpolating Filter (RCF), a
programmable Cascaded Integrator Comb (CIC) interpolating
filter, and a Numerically Controlled Oscillator/tuner (NCO).
The outputs of the four TSPs are summed and scaled on-chip.
In multichannel wideband transmitters, multiple AD6622s may
be combined using the chip’s cascadable output summation stage.
Each channel provides independent serial data inputs that may
be directly connected to the serial port of DSP chips. User pro-
grammable FIR filters can be used to filter linear inputs.
All control registers and coefficient values are programmed through
a generic microprocessor interface. Two microprocessor bus
modes are supported. All inputs and outputs are LVCMOS
compatible. All outputs are LVCMOS and 5 V TTL compatible.
REV. 0
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