COREPCI-XX Datasheet, PDF (7/42 Pages) Actel Corporation – CorePCI v5.41

PCI Bus
FRAMEn
IRDYn
STOPn
DEVSELn
TRDYn
SERRn
IDSEL
AD
PAR
CBE
PERRn
INTAn
REQn
GNTn
CLK
RSTn
Address Phase
State Machine
Dataphase
State Machine
DMA Controller
and
Register File
Parity
Datapath
Block
Configuration
For a complete list of signal descriptions, refer to Table 5 on page 8 and Table 6 on page 9.
Figure 2 • CorePCI Block Diagram
CorePCI v5.41
Back-End
Interface
CLK_OUT
EXT_INTn
BE_REQ
BE_GNT
DMA_GNT
STALL_MASTER
BUSY_MASTER
ERROR
DP_START
DP_START64
DP_DONE
BE_RD_RDY
RD_BE_NOW
RD_BE_NOW64
BE_WR_RDY
WR_BE_NOW[3:0]
WR_BE_NOW64[3:0]
MEM_DOUT
MEM_DIN
MEM_DEN
MEM_ADD[23:0]
RD_CYC
WR_CYC
BAR0_MEM_CYC
BAR1_CYC
CONFIG_CYC
BUSY
ERROR
EXT_INTN
CS_CONTROLN
RD_CONTROLN
WR_CONTROLN
MASTER_BE
MASTER_BE64
v4.0
7