COREPCI-XX Datasheet, PDF (1/42 Pages) Actel Corporation – CorePCI v5.41

CorePCI v5.41
Product Summary
Intended Use
• Most Flexible High-Performance PCI Offering
– Target, Master, and Master/Target, which
includes Target+DMA and Target+Master
functions
– 33 MHz or 66 MHz Performance
– 32-Bit or 64-Bit PCI Bus Widths
– Memory, I/O, and Configuration Support
• Backend Support for Synchronous DRAM, SRAM,
and I/O Subsystems
Key Features
• Two User-Configurable Base Address Registers for
Target Functions
• Interrupt Capability
• Built-in DMA Controller in all Master Functions
• Flexible Backend Data Flow Control
• Hot-Swap Extended Capabilities Support for
Compact PCI
Data Transfer Rates
• Fully Compliant Zero-Wait-State Burst (32-Bit or
64-Bit Transfer Each Cycle)
• Optional Paced Burst (Wait States Inserted
Between Transfers)
Supported Families
• ProASIC3/E
• ProASIC^{PLUS 1}
• Axcelerator
• RTAX-S
• SX
• SX-A
• RTSX-S¹
Synthesis and Simulation Support
• Synthesis: Exemplar^TM, Synopsys^® DC / FPGA Compiler^TM,
and Synplicity^®
• Simulation: Vital-Compliant VHDL Simulators and
OVI- Compliant Verilog Simulators
Macro Verification and Compliance
• Actel-Developed Testbench
• Hardware Tested
• I/O Drive Compliant in Targeted Devices
• Compliant with the PCI 2.3 Specification
Version
This datasheet defines the functionality of Version 5.41
for CorePCI.
Contents
General Description ................................................... 2
CorePCI Device Requirements ................................... 3
Utilization Statistics ................................................... 5
CorePCI IP Functional Block Diagram ....................... 6
Data Transactions ....................................................... 6
I/O Signal Descriptions ............................................... 6
CorePCI Target Function .......................................... 12
CorePCI Master Function ......................................... 17
Master Register Access ............................................. 19
System Timing .......................................................... 22
PCI Target Transactions ............................................ 22
PCI Master Transactions ........................................... 35
Backend Control of DMA Activity ........................... 38
Ordering Information .............................................. 40
List of Changes ......................................................... 41
Datasheet Categories ............................................... 41
Design Source Provided
• VHDL and Verilog-HDL Design Source
• Actel-Developed Testbench
October 2004
v4.0
1
© 2004 Actel Corporation