APA150-FG144I Datasheet, PDF (63/178 Pages) Actel Corporation – ProASICPLUS® Flash Family FPGAs

ProASIC^PLUS Flash Family FPGAs
Table 2-50 • JTAG Switching Characteristics
Description
Symbol
Min
Max
Unit
Output delay from TCK falling to TDI, TMS
t_TCKTDI
–4
4
ns
TDO Setup time before TCK rising
t_TDOTCK
10
ns
TDO Hold time after TCK rising
TCK period
t_TCKTDO
t_TCK
0
ns
100 ²
1,000
ns
RCK period
t_RCK
100
1,000
ns
Notes:
1. For DC electrical specifications of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to Table 2-22 on page 2-34 when V_DDP = 2.5 V
and Table 2-24 on page 2-38 when V_DDP = 3.3 V.
2. If RCK is being used, there is no minimum on the TCK period.
TCK
t_TCK
TMS, TDI
t_TCKTDI
TDO
t_TDOTCK
t_TCKTDO
Figure 2-27 • JTAG Operation Timing
v5.9
2-53