APA150-FG144I Datasheet, PDF (52/178 Pages) Actel Corporation – ProASICPLUS® Flash Family FPGAs

ProASIC^PLUS Flash Family FPGAs
Tristate Buffer Delays
EN
A
PAD
OTBx
35 pF
A
PAD
V_OL
50% 50%
V_OH
50%
t_DLH
t_DHL
50%
EN 50% 50%
V_DDP
PAD
50%
V_OL
t_ENZL
10%
EN
PAD
GND
50% 50%
V_OH
50%
t_ENZH
90%
Figure 2-23 • Tristate Buffer Delays
Table 2-27 • Worst-Case Commercial Conditions
V_DDP = 3.0 V, V_DD = 2.3 V, 35 pF load, T_J = 70°C
Macro Type
Description
OTB33PH
3.3 V, PCI Output Current, High Slew Rate
OTB33PN
3.3 V, High Output Current, Nominal Slew Rate
OTB33PL
3.3 V, High Output Current, Low Slew Rate
OTB33LH
3.3 V, Low Output Current, High Slew Rate
OTB33LN
3.3 V, Low Output Current, Nominal Slew Rate
OTB33LL
3.3 V, Low Output Current, Low Slew Rate
Notes:
1. t_DLH = Data-to-Pad High
2. t_DHL = Data-to-Pad Low
3. t_ENZH = Enable-to-Pad, Z to High
4. t_ENZL = Enable-to-Pad, Z to Low
Table 2-28 • Worst-Case Commercial Conditions
V_DDP = 2.3 V, V_DD = 2.3 V, 35 pF load, T_J = 70°C
Macro Type
OTB25LPHH
OTB25LPHN
OTB25LPHL
OTB25LPLH
OTB25LPLN
OTB25LPLL
Description
2.5 V, Low Power, High Output Current, High Slew Rate⁵
2.5 V, Low Power, High Output Current, Nominal Slew Rate⁵
2.5 V, Low Power, High Output Current, Low Slew Rate⁵
2.5 V, Low Power, Low Output Current, High Slew Rate⁵
2.5 V, Low Power, Low Output Current, Nominal Slew Rate⁵
2.5 V, Low Power, Low Output Current, Low Slew Rate⁵
Notes:
1. t_DLH = Data-to-Pad High
2. t_DHL = Data-to-Pad Low
3. t_ENZH = Enable-to-Pad, Z to High
4. t_ENZL = Enable-to-Pad, Z to Low
5. Low power I/O work with V_DDP = 2.5 V ±10% only. V_DDP = 2.3 V for delays.
Max.
t_DLH1
Std.
2.0
2.2
2.5
2.6
2.9
3.0
Max.
t_DHL2
Std.
2.2
2.9
3.2
4.0
4.3
5.6
Max. Max.
t_ENZH3 t_ENZL4
Std. Std.
2.2 2.0
2.4 2.1
2.7 2.8
2.8 3.0
3.2 4.1
3.3 5.5
Units
ns
ns
ns
ns
ns
ns
Max.
t_DLH1
Std.
2.0
2.4
2.9
2.7
3.5
4.0
Max.
t_DHL2
Std.
2.1
3.0
3.2
4.6
4.2
5.3
Max.
t_ENZH3
Std.
2.3
2.7
3.1
3.0
3.8
4.2
Max.
t_ENZL4
Std.
2.0
2.1
2.7
2.6
3.8
5.1
Units
ns
ns
ns
ns
ns
ns
2-42
v5.9