A54SX16A2PQG208 Datasheet, PDF (56/108 Pages) Actel Corporation – SX-A Family FPGAs

SX-A Family FPGAs
Table 2-29 • A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions V_CCA = 2.25 V, V_CCI = 2.25 V, T_J = 70°C)
–3 Speed* –2 Speed –1 Speed
Std. Speed
–F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
t_HCKH
Input Low to High
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0 ns
t_HCKL
Input High to Low
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0 ns
t_HPWH
Minimum Pulse Width High
t_HPWL
Minimum Pulse Width Low
t_HCKSW
Maximum Skew
t_HP
Minimum Period
f_HMAX
Maximum Frequency
Routed Array Clock Networks
1.4
1.6
1.8
2.1
2.9
ns
1.4
1.6
1.8
2.1
2.9
ns
0.6
0.6
0.7
0.8
1.3 ns
2.8
3.2
3.6
4.2
5.8
ns
357
313
278
238
172 MHz
t_RCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.5
2.9
3.4
4.7 ns
t_RCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
2.1
2.4
2.7
3.2
4.4 ns
t_RCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
2.4
2.7
3.1
3.6
5.1 ns
t_RCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
2.2
2.5
2.8
3.3
4.6 ns
t_RCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
2.5
2.9
3.2
3.8
5.3 ns
t_RCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
2.4
2.7
3.1
3.6
5.0 ns
t_RPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
t_RPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
t_RCKSW
Maximum Skew (Light Load)
1.0
1.1
1.3
1.5
2.1 ns
t_RCKSW
Maximum Skew (50% Load)
0.9
1.0
1.2
1.4
1.9 ns
t_RCKSW
Maximum Skew (100% Load)
0.9
1.0
1.2
1.4
1.9 ns
Note: *All –3 speed grades have been discontinued.
2-36
v5.3