A54SX16A2PQG208 Datasheet, PDF (51/108 Pages) Actel Corporation – SX-A Family FPGAs

SX-A Family FPGAs
Table 2-25 • A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions V_CCA = 2.25 V, V_CCI = 2.25 V, T_J = 70°C)
–3 Speed¹ –2 Speed –1 Speed
Std. Speed
–F Speed
Parameter
Description
2.5 V LVCMOS Output Module Timing ^{2, 3}
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t_DLH
Data-to-Pad Low to High
3.4
3.9
4.5
5.2
7.3 ns
t_DHL
Data-to-Pad High to Low
2.6
3.0
3.3
3.9
5.5 ns
t_DHLS
Data-to-Pad High to Low—low slew
11.6
13.4
15.2
17.9
25.0 ns
t_ENZL
Enable-to-Pad, Z to L
2.4
2.8
3.2
3.7
5.2 ns
t_ENZLS
Data-to-Pad, Z to L—low slew
11.8
13.7
15.5
18.2
25.5 ns
t_ENZH
Enable-to-Pad, Z to H
3.4
3.9
4.5
5.2
7.3 ns
t_ENLZ
Enable-to-Pad, L to Z
2.1
2.5
2.8
3.3
4.7 ns
t_ENHZ
d_TLH4
d_THL4
d_THLS4
Enable-to-Pad, H to Z
Delta Low to High
Delta High to Low
Delta High to Low—low slew
2.6
0.031
0.017
0.057
3.0
0.037
0.017
0.06
3.3
0.043
0.023
0.071
3.9
0.051
0.023
0.086
5.5 ns
0.071 ns/pF
0.037 ns/pF
0.117 ns/pF
Note:
1. All –3 speed grades have been discontinued.
2. Delays based on 35 pF loading.
3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCI value into the following equation:
Slew Rate [V/ns] = (0.1*V_CCI – 0.9*V_CCI)/ (C_load * d_T[LH|HL|HLS])
where C_load is the load capacitance driven by the I/O in pF
d_T[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
v5.3
2-31