A1020B-2PLG44I Datasheet, PDF (54/98 Pages) Actel Corporation – HiRel FPGAs

A32200DX Timing Characteristics (continued)
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max. Units
Input Module Propagation Delays
t_INPY
Input Data Pad to Y
t_INGO
Input Latch Gate-to-Output
t_INH
Input Latch Hold
t_INSU
Input Latch Setup
t_ILA
Latch Active Pulse Width
Input Module Predicted Routing Delays¹
1.9
2.6
ns
4.6
6.0
ns
0.0
0.0
ns
0.7
0.9
ns
6.1
8.1
ns
t_IRD1
FO=1 Routing Delay
t_IRD2
FO=2 Routing Delay
t_IRD3
FO=3 Routing Delay
t_IRD4
FO=4 Routing Delay
t_IRD5
FO=8 Routing Delay
Global Clock Network
2.6
3.5
ns
3.4
4.6
ns
4.6
6.1
ns
5.4
7.2
ns
7.0
9.3
ns
t_CKH
Input Low to High
FO=32
FO=635
7.3
9.8
ns
8.5
11.3
ns
t_CKL
Input High to Low
FO=32
FO=635
7.2
9.6
ns
9.3
12.5
ns
t_PWH
Minimum Pulse Width High
FO=32
3.2
FO=635
3.9
4.3
ns
5.2
ns
t_PWL
Minimum Pulse Width Low
FO=32
3.2
FO=635
3.9
4.3
ns
5.2
ns
t_CKSW
Maximum Skew
FO=32
1.8
2.4
ns
FO=635
1.8
2.4
ns
t_SUEXT
Input Latch External Setup
FO=32
0.0
FO=635
0.0
0.0
ns
0.0
ns
t_HEXT
Input Latch External Hold
FO=32
3.0
FO=635
3.8
4.0
ns
5.1
ns
t_P
Minimum Period (1/fmax)
FO=32
5.8
FO=635
6.8
7.7
ns
9.1
ns
f_HMAX
Maximum Datapath Frequency FO=32
172
130
MHz
FO=635
147
110
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
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