A1020B-2PLG44I Datasheet, PDF (52/98 Pages) Actel Corporation – HiRel FPGAs

A32200DX Timing Characteristics
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
Logic Module Combinatorial Functions
t_PD
Internal Array Module Delay
t_PDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays¹
2.8
3.8
ns
3.4
4.6
ns
t_RD1
t_RD2
t_RD3
t_RD4
t_RD5
t_RDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
1.6
2.1
ns
2.3
3.1
ns
2.9
3.9
ns
3.5
4.7
ns
6.2
8.2
ns
0.8
1.1
ns
Logic Module Sequential Timing Characteristics
t_CO
Flip-Flop Clock-to-Output
3.2
4.2
ns
t_GO
Latch Gate-to-Output
2.8
3.8
ns
t_SU
Flip-Flop (Latch) Setup Time
0.5
0.6
ns
t_H
Flip-Flop (Latch) Hold Time
0.0
0.0
ns
t_RO
Flip-Flop (Latch) Reset to Output
3.2
4.2
ns
t_SUENA
Flip-Flop (Latch) Enable Setup
0.9
1.2
ns
t_HENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
t_WCLKA
Flip-Flop (Latch) Clock Active Pulse Width
4.3
5.8
ns
t_WASYN
Flip-Flop (Latch) Asynchronous Pulse Width
5.7
7.6
ns
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
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