A10V20B-PL84C Datasheet, PDF (53/98 Pages) Actel Corporation – Highly Predictable Performance with 100 Automatic Placement and Routing

A32200DX Timing Characteristics (continued)
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
Parameter Description
Min.
Max.
Synchronous SRAM Operations
t_RC
Read Cycle Time
t_WC
Write Cycle Time
t_RCKHL
Clock High/Low Time
t_RCO
Data Valid After Clock High/Low
t_ADSU
Address/Data Setup Time
t_ADH
Address/Data Hold Time
t_RENSU
t_RENH
Read Enable Setup
Read Enable Hold
t_WENSU
t_WENH
Write Enable Setup
Write Enable Hold
t_BENS
Block Enable Setup
t_BENH
Block Enable Hold
Asynchronous SRAM Operations
t_RPD
Asynchronous Access Time
t_RDADV
Read Address Valid
t_ADSU
t_ADH
Address/Data Setup Time
Address/Data Hold Time
t_RENSUA
t_RENHA
Read Enable Setup to Address Valid
Read Enable Hold
t_WENSU
t_WENH
Write Enable Setup
Write Enable Hold
t_DOH
Data Out Hold Time
8.8
8.8
4.4
4.4
2.1
0.0
0.8
4.4
3.5
0.0
3.6
0.0
10.6
11.5
2.1
0.0
0.8
4.4
3.5
0.0
1.6
HiRel FPGAs
‘Std’ Speed
Min.
Max.
Units
11.8
ns
11.8
ns
5.9
ns
5.9
ns
2.8
ns
0.0
ns
1.1
ns
5.9
ns
4.7
ns
0.0
ns
4.8
ns
0.0
ns
14.1
ns
15.3
ns
2.8
ns
0.0
ns
1.1
ns
5.9
ns
4.7
ns
0.0
ns
2.1
ns
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