A10V20B-PL84C Datasheet, PDF (36/98 Pages) Actel Corporation – Highly Predictable Performance with 100 Automatic Placement and Routing

A1425A Timing Characteristics
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Logic Module Propagation Delays¹
t_PD
Internal Array Module
t_CO
Sequential Clock to Q
t_CLR
Asynchronous Clear to Q
Logic Module Predicted Routing Delays²
t_RD1
FO=1 Routing Delay
t_RD2
FO=2 Routing Delay
t_RD3
FO=3 Routing Delay
t_RD4
FO=4 Routing Delay
t_RD8
FO=8 Routing Delay
Logic Module Sequential Timing
t_SUD
t_HD
t_SUENA
t_HENA
t_WASYN
t_WCLKA
t_A
f_MAX
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
Input Module Propagation Delays
Min.
0.9
0.0
0.9
0.0
3.8
3.8
7.9
Max.
3.0
3.0
3.0
1.3
1.9
2.1
2.6
4.2
125
Min.
1.0
0.0
1.0
0.0
4.4
4.4
9.3
Max.
Units
3.5
ns
3.5
ns
3.5
ns
1.5
ns
2.1
ns
2.5
ns
2.9
ns
4.9
ns
ns
ns
ns
ns
ns
ns
ns
100
MHz
t_INY
Input Data Pad to Y
t_ICKY
Input Reg IOCLK Pad to Y
t_OCKY
Output Reg IOCLK Pad to Y
t_ICLRY
Input Asynchronous Clear to Y
t_OCLRY
Output Asynchronous Clear to Y
Input Module Predicted Routing Delays^{1, 3}
4.2
4.9
ns
7.0
8.2
ns
7.0
8.2
ns
7.0
8.2
ns
7.0
8.2
ns
t_IRD1
FO=1 Routing Delay
1.3
1.5
ns
t_IRD2
FO=2 Routing Delay
1.9
2.1
ns
t_IRD3
FO=3 Routing Delay
2.1
2.5
ns
t_IRD4
FO=4 Routing Delay
2.6
2.9
ns
t_IRD8
FO=8 Routing Delay
4.2
4.9
ns
Notes:
1. For dual-module macros, use t_PD + t_RD1 + t_PDn , t_CO + t_RD1 + t_PDn , or t_PD1 + t_RD1 + t_SUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
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