A1225XLV-PQ100C Datasheet, PDF (44/84 Pages) Actel Corporation – Integrator Series FPGAs: 1200XL and 3200DX Families

Integrator Series FPGAs: 1200XL and 3200DX Families
A32140DX Timing Characteristics
(Worst-Case Commercial Conditions V_CC = 4.75 V, T_J = 70°C)
‘–2 Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Logic Module Propagation Delays¹
Combinatorial Functions
t_PD
Internal Array Module Delay
t_PDD
Internal Decode Module Delay
Predicted Routing Delays²
t_RD1
FO=1 Routing Delay
t_RD2
FO=2 Routing Delay
t_RD3
FO=3 Routing Delay
t_RD4
FO=4 Routing Delay
t_RD5
FO=8 Routing Delay
t_RDD
Decode-to-Output Routing Delay
Sequential Timing Characteristics^{3, 4}
t_CO
t_GO
t_SU
t_H
t_RO
t_SUENA
t_HENA
t_WCLKA
t_WASYN
Flip-Flop Clock-to-Output
Latch Gate-to-Output
Flip-Flop (Latch) Set-Up Time
0.3
Flip-Flop (Latch) Hold Time
0.0
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Set-Up
0.6
Flip-Flop (Latch) Enable Hold
0.0
Flip-Flop (Latch) Clock Active Pulse Width 2.6
Flip-Flop (Latch) Asynchronous Pulse Width _4.1
Max.
1.8
1.9
1.0
1.4
1.8
2.2
3.8
0.5
2.1
1.8
2.1
Min.
0.4
0.0
0.9
0.0
3.5
5.5
Max.
2.3
2.5
1.3
1.9
2.4
2.9
5.0
0.7
2.8
2.3
2.8
Min.
0.47
0.0
1.0
0.0
4.1
6.5
Max.
2.8
3.0
1.6
2.2
2.8
3.4
5.9
0.78
3.3
2.8
3.3
‘–F’ Speed
Min. Max.
3.6
3.8
2.0
2.8
3.7
4.5
7.7
1.0
4.3
3.6
0.6
0.0
4.3
1.3
0.0
5.4
8.4
3.3V ‘Std’
Speed
Min. Max. Units
3.2
ns
3.5
ns
1.8
ns
2.5
ns
3.3
ns
4.0
ns
7.0
ns
0.91 ns
3.9
ns
3.2
ns
0.55
ns
0.0
ns
3.9
ns
1.17
ns
0.0
ns
4.82
ns
7.6
ns
Notes:
1. For dual-module macros, use t_PD1 + t_RD1 + t_PDn, t_CO + t_RD1 + t_PDn, or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4. Set-Up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal set-up (hold) time.
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Discontinued – v3.0