A1225XLV-PQ100C Datasheet, PDF (40/84 Pages) Actel Corporation – Integrator Series FPGAs: 1200XL and 3200DX Families

Integrator Series FPGAs: 1200XL and 3200DX Families
A32100DX Timing Characteristics
(Worst-Case Commercial Conditions V_CC = 4.75 V, T_J = 70°C)
‘–3 Speed
‘–2 Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
3.3V ‘Std’
Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic ModulePropagation Delays
Combinatorial Functions
t_PD
Internal Array Module Delay
t_PDD
Internal Decode Module Delay
Predicted Module Routing Delays
2.2
2.6
3.0
3.5
5.2
4.1 ns
2.4
2.7
3.1
3.7
5.7
4.3 ns
t_RD1
FO=1 Routing Delay
t_RD2
FO=2 Routing Delay
t_RD3
FO=3 Routing Delay
t_RD4
FO=4 Routing Delay
t_RD5
FO=8 Routing Delay
t_RDD
Decode-to-Output Routing Delay
Sequential Timing Characteristics
1.0
1.1
1.3
1.4
1.7
1.9
1.8
2.1
2.5
2.4
2.7
3.1
4.2
5.0
5.6
0.3
0.37
0.4
1.5
3.3
1.7 ns
2.2
4.3
2.5 ns
2.9
5.2
3.4 ns
3.7
6.5
4.3 ns
6.6
10.0
7.7 ns
0.5
0.4
0.6 ns
t_CO
t_GO
t_SU
t_H
t_RO
t_SUENA
t_HENA
t_WCLKA
t_WASYN
Flip-Flop Clock-to-Output
2.2
2.6
3.0
3.5
5.0
4.1 ns
Latch Gate-to-Output
2.2
2.6
3.0
3.5
5.0
4.1 ns
Flip-Flop (Latch) Set-Up Time
0.3
0.37
0.4
0.5
0.7
0.6
ns
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Reset to Output
2.2
2.6
3.0
3.5
5.0
4.1 ns
Flip-Flop (Latch) Enable Set-Up
0.6
0.75
0.9
1.0
1.4
0.85
ns
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Clock Active Pulse Width 3.1
3.7
4.2
4.9
7.0
5.7
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
4.1
4.8
5.4
6.4
7.0
7.5
ns
40
Discontinued – v3.0