A54SX32-TQ144 Datasheet, PDF (33/64 Pages) Actel Corporation – SX Family FPGAs

SX Family FPGAs
Table 1-19 • A54SX16P Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, V_CCR = 4.75 V, V_CCA,V_CCI = 3.0 V, T_J = 70°C)
'–3' Speed '–2' Speed '–1' Speed
'Std' Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Network
t_HCKH
Input LOW to HIGH (pad to R-Cell input)
1.2
1.4
1.5
1.8
ns
t_HCKL
Input HIGH to LOW (pad to R-Cell input)
1.2
1.4
1.6
1.9
ns
t_HPWH
Minimum Pulse Width HIGH
1.4
1.6
1.8
2.1
ns
t_HPWL
Minimum Pulse Width LOW
1.4
1.6
1.8
2.1
ns
t_HCKSW
Maximum Skew
0.2
0.2
0.3
0.3
ns
t_HP
Minimum Period
2.7
3.1
3.6
4.2
ns
f_HMAX
Maximum Frequency
350
320
280
240 MHz
Routed Array Clock Networks
t_RCKH
Input LOW to HIGH (light load)
(pad to R-Cell input)
1.6
1.8
2.1
2.5
ns
t_RCKL
Input HIGH to LOW (Light Load)
(pad to R-Cell input)
1.8
2.0
2.3
2.7
ns
t_RCKH
Input LOW to HIGH (50% load)
(pad to R-Cell input)
1.8
2.1
2.5
2.8
ns
t_RCKL
Input HIGH to LOW (50% load)
(pad to R-Cell input)
2.0
2.2
2.5
3.0
ns
t_RCKH
Input LOW to HIGH (100% load)
(pad to R-Cell input)
1.8
2.1
2.4
2.8
ns
t_RCKL
Input HIGH to LOW (100% load)
(pad to R-Cell input)
2.0
2.2
2.5
3.0
ns
t_RPWH
Min. Pulse Width HIGH
t_RPWL
Min. Pulse Width LOW
t_RCKSW
Maximum Skew (light load)
t_RCKSW
Maximum Skew (50% load)
t_RCKSW
Maximum Skew (100% load)
TTL Output Module Timing
2.1
2.4
2.7
3.2
ns
2.1
2.4
2.7
3.2
ns
0.5
0.5
0.5
0.7
ns
0.5
0.6
0.7
0.8
ns
0.5
0.6
0.7
0.8
ns
t_DLH
Data-to-Pad LOW to HIGH
2.4
2.8
3.1
3.7
ns
t_DHL
Data-to-Pad HIGH to LOW
2.3
2.9
3.2
3.8
ns
t_ENZL
Enable-to-Pad, Z to L
3.0
3.4
3.9
4.6
ns
t_ENZH
Enable-to-Pad, Z to H
3.3
3.8
4.3
5.0
ns
t_ENLZ
Enable-to-Pad, L to Z
2.3
2.7
3.0
3.5
ns
t_ENHZ
Enable-to-Pad, H to Z
2.8
3.2
3.7
4.3
ns
Note:
1. For dual-module macros, use t_PD + t_RD1 + t_PDn, t_RCO + t_RD1 + t_PDn, or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Delays based on 10 pF loading.
v3.2
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