A54SX32-TQ144 Datasheet, PDF (1/64 Pages) Actel Corporation – SX Family FPGAs

SX Family FPGAs
Leading Edge Performance
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Setup
• 0.25 ns Clock Skew
Specifications
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1,080 Flip-Flops
• 0.35 µ CMOS
SX Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Setup (external)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
A54SX08
8,000
12,000
768
512
256
130
3
Yes
–
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
84
208
100
144, 176
–
144
v3.2
™
ue
Features
• 66 MHz PCI
• CPLD and FPGA Integration
• Single-Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability
with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
A54SX16
16,000
24,000
1,452
924
528
175
3
Yes
–
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
–
208
100
176
–
–
A54SX16P
16,000
24,000
1,452
924
528
175
3
Yes
Yes
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
–
208
100
144, 176
–
–
A54SX32
32,000
48,000
2,880
1,800
1,080
249
3
Yes
–
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
–
208
–
144, 176
313, 329
–
June 2006
© 2006 Actel Corporation
i
See the Actel website for the latest version of the datasheet.