A1010B-PLG68C Datasheet, PDF (20/98 Pages) Actel Corporation – HiRel FPGAs

Sequential Timing Characteristics (continued)
Flip-Flops and Latches (1200XL/3200DX, ACT 2, and ACT 1)
D
PRE
Y
E
CLK
CLR
(Positive edge triggered)
D¹
G, CLK
E
Q
PRE, CLR
t_SUD
t_HD
t_WCLKA
t_SUENA
t_HENA
t_CO
Note:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
t_A
t_RS
t_WASYN
20