A1010B-PLG68C Datasheet, PDF (13/98 Pages) Actel Corporation – HiRel FPGAs

HiRel FPGAs
Fixed Capacitance Values for
Actel FPGAs (pF)
Device Type
r₁
routed_Clk1
A1010B
41
A1020B
69
A1240A
134
A1280A
168
A1280XL
168
A1425A
75
A1460A
165
A14100A
195
A32100DX
178
A32200DX
230
r₂
routed_Clk2
n/a
n/a
134
168
168
75
165
195
178
230
Fixed Clock Loads (s₁/s₂—ACT 3 Only)
s₁
s₂
Clock Loads on Clock Loads on
Dedicated
Dedicated
Device Type
Array Clock
I/O Clock
A1425A
160
100
A1460A
432
168
A14100A
697
228
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data values input to the
circuit. The guidelines in the table below are meant to
represent worst-case scenarios so that they can be generally
used to predict the upper limits of power dissipation.
Type
Logic modules (m)
Input switching (n)
Outputs switching (p)
First routed array clock loads (q₁)
Second routed array clock loads (q₂)
Load capacitance (C_L)
Average logic module switching rate (f_m)
Average input switching rate (f_n)
Average output switching rate (f_p)
Average first routed array clock rate (f_q1)
Average second routed array clock rate (f_q2)
Average dedicated array clock rate (f_s1)
Average dedicated I/O clock rate (f_s2)
ACT 3
80% of modules
# inputs/4
#outputs/4
40% of sequential
modules
40% of sequential
modules
35 pF
F/10
F/5
F/10
F/2
F/2
F
F
3200DX/ACT 2/1200XL
80% of modules
# inputs/4
#outputs/4
40% of sequential
modules
40% of sequential
modules
35 pF
F/10
F/5
F/10
F
F/2
n/a
n/a
ACT 1
90% of modules
# inputs/4
#outputs/4
40% of modules
n/a
35 pF
F/10
F/5
F/10
F
n/a
n/a
n/a
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