A3PE3000-1FGG896I Datasheet, PDF (19/152 Pages) Actel Corporation – ProASIC3E Flash Family FPGAs

ProASIC3E DC and Switching Characteristics
Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued)
Differential
VMV
(V)
Static Power
P_DC2 (mW)¹
Dynamic Power
P_AC9 (µW/MHz)²
LVDS/B-LVDS/M-LVDS
2.5
2.26
1.50
LVPECL
3.3
5.71
2.17
Notes:
1. P_DC2 is the static power (where applicable) measured on VMV.
2. P_AC9 is the total dynamic power measured on V_CC and VMV.
Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹
Single-Ended
C_LOAD
(pF)
V_CCI
Static Power
Dynamic Power
(V)
P_DC3 (mW)²
P_AC10 (μW/MHz)³
3.3 V LVTTL/LVCMOS
35
3.3
–
474.70
2.5 V LVCMOS
35
2.5
–
270.73
1.8 V LVCMOS
35
1.8
–
151.78
1.5 V LVCMOS (JESD8-11)
35
1.5
–
104.55
3.3 V PCI
10
3.3
–
204.61
3.3 V PCI-X
10
3.3
–
204.61
Voltage-Referenced
3.3 V GTL
10
3.3
–
24.08
2.5 V GTL
10
2.5
–
13.52
3.3 V GTL+
10
3.3
–
24.10
2.5 V GTL+
10
2.5
–
13.54
HSTL (I)
20
1.5
7.08
26.22
HSTL (II)
20
1.5
13.88
27.22
SSTL2 (I)
30
2.5
16.69
105.56
SSTL2 (II)
30
2.5
25.91
116.60
SSTL3 (I)
30
3.3
26.02
114.87
SSTL3 (II)
30
3.3
42.21
131.76
Differential
LVDS/B-LVDS/M-LVDS
–
2.5
7.70
89.62
LVPECL
–
3.3
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output
slew.
2. P_DC3 is the static power (where applicable) measured on V_CCI.
3. P_AC10 is the total dynamic power measured on V_CC and V_CCI.
v1.2
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