ACE24C128_11 Datasheet, PDF (9/18 Pages) ACE Technology Co., LTD. – Two-wire Serial EEPROM

ACE24C128/256
Two-wire Serial EEPROM
Figure 6．Output Acknowledge
Device Addressing
The 128K/256K EEPROM device require an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure 7).
The device address word consists of a mandatory one, zero sequence for the first four most
significant bits as shown. This is common to all the EEPROM devices.
The 128/256K EEPROM use the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hard-wired input pins. The
A2,A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins
are allowed to float.
The Module package device address word also consists of a mandatory one, zero sequence for the
first four most significant bits. The next 3 bits are all zero.
The eight bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the
device will return to a standby state.
Noise protection:
Special internal circuitry place on the SDA and SCL pins prevent small noise spikes from activating the
device.
Date Security:
The ACE24C128/256 has a hardware data protect scheme that slows the user to write protect the
entire memory when the WP pin is at Vcc.
Write Operations
Byte Write:
A write operation requires two 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a
zero and the addressing device, such as a microcontroller, must terminate the write sequence with a
stop condition. At this time the EEPROM enters an internally timed write cycle, t_WR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (refer to Figure 8).
VER 1.5 9