ACE24C512C Datasheet, PDF (8/18 Pages) ACE Technology Co., LTD. – Two-wire serial EEPROM

ACE24C512C
Two-wire serial EEPROM
Soft Reset
After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following
these steps: (a) Create a start condition, (b) Clock nine cycles, and (c) create another start bit followed by
stop bit condition, as shown below. The device is ready for the next communication after the above steps
have been completed.
Figure6：Soft Reset
Device Addressing
The ACE24C512C requires an 8-bit device address word following a start condition to enable the chip for
a read or write operation (see Figure7). The device address word consists of a mandatory one-zero
sequence for the first four most-significant bits, as shown.
Figure7：Device Address
The three E2, E1, and E0 device address bits allow as many as eight devices on the same bus. These
bits must compare to their corresponding hardwired input pins.
The E2, E1, and E0 pins use an internal proprietary circuit that biases them to a logic low condition if the
pins are floating.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the
Chip will output a zero. If a compare is not made, the device will return to a standby state.
Data Security
ACE24C512C has a hardware data protection scheme that allows the user to write protect the whole
memory when the WCB pin is at V_CC.
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