AAT1415 Datasheet, PDF (23/32 Pages) Advanced Analog Technology, Inc. – FIVE-CHANNEL DC-DC CONVERTER WITH A 2.5V LDO

Advanced Analog Technology, Inc.
May 2008
AAT1415/AAT1415A
See Figure 6. soft-start mechanism. CH3 soft-start
ramp takes half the time (2,048 clock cycles) of the
other channel ramps. This allows the CH3 and CH2
output (when set to 3.3V) to track each other and rise
at nearly the same dV/dt rate on power-up. Once the
step-down output reaches its regulation point (1.5V or
1.8V typ), the CH2 output (3.3V typ) continues to rise at
the same ramp rate. See Figure 7 timing chart of
soft-start.
2.5V LDO
The 2.5V LDO regulates the VDDC voltages when the
reference voltage (VREF) is ready and VDDC voltage is
greater than 2.5V.
Fault Protection
If any DC-DC converter channel remains faulted for
100,000 clock cycles (200ms at 500kHz), then all
outputs latch off until the AAT1415/AAT1415A is
reinitialized or by cycling the input power. The
fault-detection circuitry for any channel is disabled
during its initial turn-on soft-start sequence. An
exception to the standard fault behavior is that there is
no 100,000 clock-cycle delay in entering the fault state
if the OUT1 pin is dragged below its 2.5V UVLO1
threshold or is shorted. The UVLO1 immediately
triggers and shuts down all channels. The CH1 then
continues to attempt to start. If the CH1 output short
remains, these attempts do not succeed since OUT1
remains near ground. If a soft-short or overload
remains on OUT1, the startup oscillator switches the
internal NMOS, but fault is retriggered if regulation is
not achieved by the end of the soft-start interval. If
OUT1 is dragged below the input, the overload is
supplied by the body diode of the internal synchronous
rectifier or by a Schottky diode connected from the
battery to OUT1.
Reference
Connect a 0.1µF ceramic bypass capacitor from VREF
to GND. VREF is enabled when EN1, EN2 or EN3 is
high. The AAT1415/AAT1415A has internal 1.250V
references.
Oscillator
The AAT1415/AAT1415A operating frequency is set by
an RC network (R_OSC, C_OSC) at the OSC pin. The range
of usable settings is 100kHz to 1MHz. The oscillation
frequency changes as the forced voltage (V_OSC) ramps
upward following startup. The oscillation frequency is
then constant once the main output is in regulation. At
the beginning of a cycle, the timing capacitor charge
through the resistor until it reaches VREF. The charge
time, t₁, is as follows:
t₁
≈
− R_OSC ×
C_OSC × ln(1 −
1.25
V_OSC
)
The capacitor voltage then decays to zero over
time t₂ ≈ 150ns . Choose C_OSC between 47pF and
330pF. Determine R_OSC and V_OSC. The oscillator
frequency is as follows:
f_OSC
≈
1
t₁+ t₂
Figure 5. Oscillator Circuit
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