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AAT3685 Datasheet, PDF (18/23 Pages) Advanced Analogic Technologies – Lithium-Ion/Polymer Battery Charger
AAT3685
Lithium-Ion/Polymer Battery Charger
Data Timing
The system microcontroller should assert an active
low data request pulse for minimum duration of
200ns; this is specified by TLO(DATA). Upon sensing
the rising edge of the end of the data request pulse,
Timing Diagram
the AAT3685 status data control will reply the data
word back to the system microcontroller after a
delay specified by the data report time specification
TDATA(RPT). The period of the following group of data
pulses will be specified by the TDATA specification.
SQ
CK
Data
SQPULSE
System Reset
System Start
TSYNC
TLAT
TDATA(RPT) = TSYNC + TLAT < 2.5 PDATA
TOFF > 2 PDATA
PDATA
N=1
N=2
TOFF
N=3
Thermal Considerations
The AAT3685 is packaged in a Pb-free, 3x3mm
TDFN package which can provide up to 2.0W of
power dissipation when it is properly bonded to a
printed circuit board and has a maximum thermal
resistance of 50°C/W. Many considerations should
be taken into account when designing the printed
circuit board layout, as well as the placement of the
charger IC package in proximity to other heat gen-
erating devices in a given application design. The
ambient temperature around the charger IC will
also have an affect on the thermal limits of a bat-
tery charging application. The maximum limits that
can be expected for a given ambient condition can
be estimated by the following discussion.
First, the maximum power dissipation for a given
situation should be calculated:
Eq. 4: PD = [(VIN - VBAT) · ICC + (VIN · IOP)]
Where:
PD = Total Power Dissipation by the Device
VIN = Input Voltage Level, VADP/USB
VBAT = Battery Voltage as Seen at the BAT Pin
ICC = Maximum Constant Fast Charge Current
Programmed for the Application
IOP = Quiescent Current Consumed by the
Charger IC for Normal Operation
Next, the maximum operating ambient temperature
for a given application can be estimated based on
the thermal resistance of the 3x3mm TDFN pack-
age when sufficiently mounted to a PCB layout and
the internal thermal loop temperature threshold.
Eq. 5: TA = TJ - (θJA · PD)
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3685.2006.10.1.3