Z86L04 Datasheet, PDF (14/26 Pages) Zilog, Inc. – Z8 8-Bit Cost-Effective Microcontrollers

Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
tion. The POR time allows V_CC and the oscillator circuit to
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the five
following conditions:
s Power bad to power good status
s Stop-Mode Recovery
s WDT time-out
s WDT time-out (in HALT Mode)
s WDT time-out (in STOP Mode)
Watch-Dog Timer Reset. The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator. If the permanent WDT option is select-
ed then the WDT is enabled after reset and operates in
RUN Mode, HALT mode, STOP mode and cannot be dis-
abled. If the permanent WDT option is not selected then
the WDT, when enabled by the user's software, does not
operate in STOP Mode, but it can operate in HALT Mode
by using a WDH instruction.
Zilog
Table 3. Control Register Reset Values
Reset Condition
Addr Reg. D7 D6 D5 D4 D3 D2 D1 D0 Comments
FF SPL 0 0 0 0 0 0 0 0
FE GPR 0 0 0 0 0 0 0 0
FD RP
00000000
FC FLAGS U U U U U U U U
FB IMR 0 U U U U U U U
FA IRQ
U U 0 0 0 0 0 0 IRQ3 is used
for positive
edge
detection
F9 IPR U U U U U U U U
F8* P01M U U U 0 U U 0 1
F7* P3M U U U U U U 0 0 P2 open-drain
F6* P2M 1 1 1 1 1 1 1 1 Inputs after
reset
F5 PRE0 U U U U U U U 0
F4 T0
UUUUUUUU
F3 PRE1 U U U U U U 0 0
F2 T1
UUUUUUUU
F1 TMR 0 0 0 0 0 0 0 0
Notes:
*Registers are not reset after a STOP-Mode Recovery using P27
pin. A subsequent reset will cause these control registers to be
reconfigured as shown in Table 4 and the user must avoid bus
contention on the port pins or it may affect device reliability.
14
PRELIMINARY
DS97LVO0901