YSS932 Datasheet, PDF (15/23 Pages) YAMAHA CORPORATION – 96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP

YSS932
Control Register / Register Map
The decoding system is controlled by reading and writing the control registers as shown below through
microprocessor interfaces (/CS, SCK, SI, SO).
All control registers are reset to "0" by initial clear (/IC=L).
Address
Name
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x00 AUTO/DSN AUTOMOD
DSNIGN
DSN2-0
0x01
MUTE
LMUTEN CMUTEN RMUTEN RSMUTEN LSMUTEN LFEMUTEN DSPMUTEN AMOFF
0x02
SDIA
SDIACKSEL SDIASEL
SDIAFMT1-0
SDIABIT1-0
SDIAWP SDIABP
0x03
SDOA
SDOAFMT1-0
SDOABIT1-0
SDOAWP SDOABP
0x04
OPORT
OPORT7-0
0x05
IPORT
IPORT7-0
0x06
(TEST)
0x07
(TEST)
0x08
PCM
PLDECMOD1-0 PCMDLY LROUT
0x09 NOISE LEVEL
NOISELEV7-0
0x0A CENTER DELAY
CDELAY2-0
0x0B SURROUND DELAY
SRDELAY3-0
0x0C
NOISE
NOISE PN/WN IMPULSE
DIMCFG2-0
0x0D
FS
CWCFG2-0
SRFIL1-0
FS2-0
0x0E L VOLUME
LVOL7-0
0x0F C VOLUME
CVOL7-0
0x10 R VOLUME
RVOL7-0
0x11 LS VOLUME
LSVOL7-0
0x12 RS VOLUME
RSVOL7-0
0x13 LFE VOLUME
LFEVOL7-0
0x14 COMPRESSION EMPON AIBON VOLON DITHOFF P11OFF DIALOFF
COMPMOD1-0
0x15 HDYNRNG
HDYNRNG7-0
0x16 LDYNRNG
LDYNRNG7-0
0x17
MODE
PCMMOD PLDECON RSINV
DUALMOD1-0
OUTMOD2-0
0x18
|
BITSTREAM
(described in the later section)
0x2A
0x2B
(Unused)
(Undefined)
0x2C
(Unused)
(Undefined)
0x2D
Pc
Pc7-0
0x2E DATA STREAM STREAM7 STREAM6 STREAM5 STREAM4 STREAM3 STREAM2 STREAM1 STREAM0
0x2F
STATUS
DTSDATA AC3DATA 2/0MODE SURENC KARAOKE MUTE
CRC NONPCM
0x30
ZERO
ZEROFLG
ZERO6-0
0x31
(TEST)
0x32
MPCNT_H
MPLOAD MPCLEARN
MPCNT11-8
0x33
MPCNT_L
MPCNT7-0
0x34
SDIB
SDIBCKSEL SDIBSEL
SDIBFMT1-0
SDIBBIT1-0
SDIBWP SDIBBP
0x35
SDOB
SDOBCKSEL
SDOBFMT1-0
SDOBBIT1-0
SDOBWP SDOBBP
0x36
ERAM
OVFSEL JMPSEL
RASREF ERAMMOD ERAMSEL1-0
0x37
(TEST)
15