CG6263AM Datasheet, PDF (1/12 Pages) Weida Semiconductor, Inc. – 2Mb (128K x 16) Pseudo Static RAM

PRELIMINARY
CG6263AM
2Mb (128K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.70V–3.30V
• Access Time: 70ns
• Ultra-low active power
— Typical active current: 2.0mA @ f = 1 MHz
— Typical active current: 13mA @ f = f_max
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48 Ball BGA Package
Functional Description^[1]
The CG6263AM is a high-performance CMOS Pseudo static
RAM organized as 128K words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life^® (MoBL) in
portable applications such as cellular telephones. The device
can be put into standby mode reducing power consumption by
more than 99% The device can also be put into standby mode
when deselected (CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O₀ through I/O₁₅) are placed in a
high-impedance state when: deselected (CE HIGH ), outputs
are disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW). The addresses must not
be toggled once the read is started on the device.
Writing to the device is accomplished by taking Chip Enables
(CE LOW ) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O₀ through
I/O₇), is written into the location specified on the address pins
(A₀ through A₁₇). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₇).
Reading from the device is accomplished by taking Chip
Enables (CE LOW) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O₀ to I/O₇. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O₈ to
I/O₁₅. See the truth table at the back of this datasheet for a
complete description of read and write modes
Logic Block Diagram
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
128K × 16
A₅
RAM Array
A₄
A₃
A₂
A₁
A₀
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
Power- Down
Circuit
BHE
BLE
BHE
WE
CE
OE
BLE
CE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Weida Semiconductor, Inc.
38-XXXXX
Revised Feb 2004