SN74ACT8994 Datasheet, PDF (1/11 Pages) Texas Instruments – DIGITAL BUS MONITOR IEEE STD 1149.1 JTAG SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SN74ACT8994
DIGITAL BUS MONITOR
IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER
SCAS196E – JULY 1990 – REVISED DECEMBER 1996
D Member of the Texas Instruments SCOPE ™
Family of Testability Products
D Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
D Contains a 1024-Word by 16-Bit
Random-Access Memory (RAM) to Store
the States of a Digital Bus
D Test Operations Are Synchronous to the
Test Clock or System Clock(s)
D Contains Texas Instruments Event
Qualification Module for Real-Time System
Test
D Eight Protocols for On-Line Signal
Monitoring and Test Operations
D Inputs Are TTL-Voltage Compatible
D Performs Parallel-Signature Analysis (PSA)
of Data Inputs With User-Definable
Feedback
D Data Inputs Are Maskable During PSA
Operations
D Cascaded PSA Mode Allows Compression
of Parallel Data Paths Greater Than 16 Bits
in Width
D Direct Memory Access (DMA) Speeds
Memory and Register File Read/Write
Operations
D Power-Down Mode When RAM Is Idling
Reduces Power Dissipation
D EPIC ™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
D Packaged in 28-Pin Plastic Chip Carriers
FN PACKAGE
(TOP VIEW)
D1
D0
CLK1
CLK2
CLK3
TMS
TCK
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
D8
D9
D10
D11
D12
D13
D14
description
The SN74ACT8994 digital bus monitor (DBM) is a member of the Texas Instruments SCOPE™ testability
integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary
scan to facilitate testing of complex circuit-board assemblies. The DBM is a boundary-scannable device
designed to monitor and/or store the values of a digital bus up to 16 bits in width. It resides in parallel with the
bus being monitored.
Data at the D-input pins can be stored in a scannable random-access memory (RAM). Up to 1024 words of
16 bits can be stored. A parallel-signature analysis (PSA) can be performed on the data or on the contents of
memory. The PSA operations use a linear-feedback shift-register technique to compress data into a signature.
The user can configure the device to mask any combination of data inputs and control the feedback used during
PSA operations.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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