PCS2P5T907A Datasheet, PDF (1/21 Pages) PulseCore Semiconductor – 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer

September 2006
rev 0.2
PCS2P5T907A
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Features
• Guaranteed Low Skew < 25pS (max)
• Very low duty cycle distortion
• High speed propagation delay < 2.5nS. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V V_DDQ for HSTL interface
• Hot Insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or
LVEPECL input interface
• Selectable differential or single-ended inputs and
ten single ended outputs
• 2.5V Supply Voltage
• Available in TSSOP Package
Functional Description
The PCS2P5T907A 2.5V single data rate (SDR) clock
buffer is a user-selectable single-ended or differential input
to ten single-ended outputs buffer built on advanced metal
CMOS technology. The SDR clock buffer fanout from a
single or differential input to ten single-ended outputs
reduces the loading on the preceding driver and provides
an efficient clock distribution network. The PCS2P5T907A
can act as a translator from a differential HSTL, eHSTL,
1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V
LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3-level input signals
that may be hard-wired to appropriate high-mid-low levels.
The PCS2P5T907A has two output banks that can be
asynchronously enabled/ disabled. Multiple power and
grounds reduce noise.
Applications:
PCS2P5T907A is targeted towards Clock and signal
distribution applications.
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: [phone] • Fax: [phone]
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.