NLAST4051_06 Datasheet, PDF (1/12 Pages) ON Semiconductor – Analog Multiplexer/ Demultiplexer

NLAST4051
Analog Multiplexer/
Demultiplexer
TTL Compatible, Single−Pole, 8−Position
Plus Common Off
The NLAST4051 is an improved version of the MC14051 and
MC74HC4051 fabricated in sub−micron Silicon Gate CMOS technology
for lower R_DS(on) resistance and improved linearity with low current.
This device may be operated either with a single supply or dual supply up
to ±3 V to pass a 6 V_PP signal without coupling capacitors.
When operating in single supply mode, it is only necessary to tie
V_EE, pin 7 to ground. For dual supply operation, V_EE is tied to a
negative voltage, not to exceed maximum ratings. Translation is
provided in the device, the Address and Inhibit are standard TTL level
compatible. For CMOS compatibility see NLAS4051. Pin for pin
compatible with all industry standard versions of ‘4051.’
Features
• Improved R_DS(on) Specifications
• Pin for Pin Replacement for MAX4051 and MAX4051A
− One Half the Resistance Operating at 5.0 V
• Single or Dual Supply Operation
− Single 3.0 − 5.0 V Operation, or Dual ±3 V Operation
− With V_CC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
− No Translators Needed
− Address and Inhibit Logic are Over−Voltage Tolerant and May Be
− Driven Up +6 V Regardless of V_CC
• Address and Inhibit Pins Standard TTL Compatible
− Greatly Improved Noise Margin Over MAX4051 and MAX4051A
− True TTL Compatibility V_IL = 0.8 V, V_IH = 2.0 V
• Improved Linearity Over Standard HC4051 Devices
• Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
• Pb−Free Packages are Available*
V_CC NO₂ NO₄ NO₀ NO₆ ADD_C ADD_B ADD_A
16 15 14 13 12 11 10 9
http://onsemi.com
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
NLAST4051
AWLYWW
1
1
16
TSSOP−16
AST
DT SUFFIX
4051
CASE 948F
ALYWG
1
G
1
16
QSOP−16
NLAST
QS SUFFIX
CASE 492
4051
ALYW
1
1
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
1
2
3
4
5
6
7
8
NO₁ NO₃ COM NO₇ NO₅ Inhibit V_EE GND
Figure 1. Pin Connection
(Top View)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
April, 2006 − Rev. 4
Publication Order Number:
NLAST4051/D