NL17SZ74_06 Datasheet, PDF (1/6 Pages) ON Semiconductor – Single D Flip Flop

NL17SZ74
Single D Flip Flop
The NL17SZ74 is a high performance, full function Edge triggered
D Flip Flop, with all the features of a standard logic device such as the
74LCX74.
Features
• Extremely High Speed: t_PD 2.6 ns (typical) at V_CC = 5.0 V
• Designed for 1.65 V to 5.5 V V_CC Operation
• 5.0 V Tolerant Inputs − Interface Capability with 5.0 V TTL Logic
• LVTTL Compatible
• LVCMOS Compatible
• 24 mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current (10 mA) Substantially Reduces
System Power Requirements
• Replacement for NC7SZ74
• Tiny Ultra Small Package Only 2.1 X 3.0 mm
• High ESD Ratings: 2000 V Human Body Model
High ESD Ratings: 200 V Machine Model
• Chip Complexity: FET = 64
• Pb−Free Packages are Available
TRUTH TABLE
Inputs
Outputs
PR CLR CP D Q Q
Operating Mode
L HX XHL
H L X X LH
L
L
X
X
HH
Asynchronous Set
Asynchronous Clear
Undetermined
H
H
↑
h
H
L
HH↑
l
LH
Load and Read Register
H
H
↑
X NC NC
Hold
H
= High Voltage Level
h
= High Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
L
= Low Voltage Level
l
= Low Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
NC
= No Change
X
= High or Low Voltage Level and Transitions are Acceptable
↑
= Low−to−High Transition
↑
= Not a Low−to−High Transition
For I_CC reasons, DO NOT FLOAT Inputs
http://onsemi.com
MARKING
DIAGRAM
US8
US SUFFIX
CASE 493
MH M
G
M
= Date Code
G
= Pb−Free Package
PINOUT DIAGRAM
CP
D
Q
GND
18
2
7
3
6
4
5
V_CC
PR
CLR
Q
LOGIC DIAGRAM
PR
D
CP
CLR
7
2
5
Q
1
3
Q
6
V_CC = 8, GND = 4
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
April, 2006 − Rev. 4
Publication Order Number:
NL17SZ74/D