NL17SZ125_05 Datasheet, PDF (1/8 Pages) ON Semiconductor – Non-Inverting 3-State Buffer

NL17SZ125
Non−Inverting 3−State Buffer
The NL17SZ125 is a high performance non−inverting buffer operating
from a 1.65 V to 5.5 V supply.
• Extremely High Speed: t_PD 2.6 ns (typical) at V_CC = 5.0 V
• Designed for 1.65 V to 5.5 V V_CC Operation
• Overvoltage Tolerant Inputs and Outputs
• LVTTL Compatible − Interface Capability With 5.0 V TTL Logic
with V_CC = 3.0 V
• LVCMOS Compatible
• 24 mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current Substantially Reduces System
Power Requirements
• 3−State OE Input is Active−Low
• Replacement for NC7SZ125
• Chip Complexity = 36 FETs
• Pb−Free Packages are Available
OE 1
IN A 2
GND 3
5 V_CC
4 OUT Y
http://onsemi.com
MARKING
DIAGRAM
SC−88A (SOT−353)
DF SUFFIX
CASE 419A
M0 M G
G
SOT−553
XV5 SUFFIX
CASE 463B
M0 MG
G
M0 = Specific Device Code
D = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
Figure 1. Pinout (Top View)
OE
EN
IN A
OUT Y
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2005
1
September, 2005 − Rev. 5
PIN ASSIGNMENT
1
OE
2
IN A
3
GND
4
OUT Y
5
V_CC
FUNCTION TABLE
OE Input
A Input
Y Output
L
L
L
L
H
H
H
X
Z
X = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
NL17SZ125/D