NL17SHT126 Datasheet, PDF (1/5 Pages) ON Semiconductor – Noninverting Buffer CMOS Logic Level Shifter

NL17SHT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The NL17SHT126 is a single gate noninverting 3−state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The NL17SHT126 requires the 3−state control input (OE) to be set
Low to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the high−voltage power supply.
The NL17SHT126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the NL17SHT126 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when
V_CC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
• High Speed: t_PD = 3.5 ns (Typ) at V_CC = 5 V
• Low Power Dissipation: I_CC = 1 mA (Max) at T_A = 25°C
• TTL−Compatible Inputs: V_IL = 0.8 V; V_IH = 2 V
• CMOS−Compatible Outputs: V_OH > 0.8 V_CC; V_OL < 0.1 V_CC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• These are Pb−Free Devices
IN A 1
GND ²
OE ³
5 V_CC
4 OUT Y
http://onsemi.com
MARKING
DIAGRAM
SOT−953
CASE 527AE
RM
1
R = Specific Device Code
M = Month Code
PIN ASSIGNMENT
1
IN A
2
GND
3
OE
4
OUT Y
5
V_CC
A Input
L
H
X
FUNCTION TABLE
OE Input
Y Output
H
L
H
H
L
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 1. Pinout (Top View)
OE
OUT Y
IN A
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2011
1
August, 2011 − Rev. 0
Publication Order Number:
NL17SHT126/D