NJW1195 Datasheet, PDF (1/3 Pages) New Japan Radio – 4-Channel Electronic Volume with Input Selector

NJW1195
4-Channel Electronic Volume with Input Selector
s GENERAL DESCRIPTION
The NJW1195 is a 4-channel electronic volume with 4-in
2-out stereo audio selector. It performs low noise and low
distortion characteristics with resistance ladder circuit.
The NJW1195 is also available for 2-channel differential
transmission electronic volume with 2-in 1-out stereo audio
selector by a differential transmission select function.
All of functions are controlled via three-wired serial bus.
Selectable 4-Chip address is available for using four chips
on same serial bus line.
It’s suitable for two-channel stereo system and or
multi-channel audio system.
s PACKAGE OUTLINE
NJW1195V
s FEATURES
q Operating Voltage
q 3-Wired Serial Control
q Selectable 4-Chip Address
q Low Output Noise
q Low Distortion
q 4in 2out Stereo Signal Selector
q Volume
q Differential transmission select function
q Channel Separation
q Zero Cross Detection
q Bi-CMOS Technology
q Package Outline
±4.5 to ±7.5V
Chip Address Select Function
Available for using four chips on same serial bus line
-118dBV typ.
0.0003% typ. at Vin=1Vrms (Differential transmission)
+31.5 to –95dB / 0.5dB step, Mute
-120dB typ.
SSOP32
s BLOCK DIAGRAM
Application example 1
4-channel electronic volume
with 4-in 2-out stereo audio selector (DIFF pin = Low)
Application example 2
2-channel differential transmission electronic volume with
2-in 1-out stereo audio selector (DIFF pin = High)
4-input 2-output
stereo selector
(Single)
4-channel Electronic Volume (Single)
Main Volume :+31.5 to -95dB / 0.5dBstep
2-input 1-output
stereo selector
(Differential)
2-channel Electronic Volume (Differential)
Main Volume :+31.5 to -95dB / 0.5dBstep
InA1
InA2
InA3
InA4
InB1
InB2
InB3
InB4
Mute
Out1A
Mute
Mute
Mute
Zero Cross
Detection
Control Logic
Out2A
Out1B
Out2B
DIFF=Low
Data Latch ADR1
Clock ADR0
Ver 1.2 for web
InA1+
InA1-
InA2+
InA2-
Mute
OutA+
OutA-
InB1+
InB1-
InB2+
InB2-
Mute
OutB+
OutB-
Zero Cross
Detection
Control Logic
DIFF=High
Data Latch ADR1
Clock ADR0
–1–