932SQ420D Datasheet, PDF (27/28 Pages) Integrated Device Technology – 64-pin TSSOP and MLF packages

932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
Revision History
Rev.
A
B
C
D
E
F
G
H
J
Issue Date
9/20/2010
3/1/2011
3/9/2011
4/28/2011
7/26/2011
9/20/2011
12/8/2011
4/18/2012
1/7/2015
Who Description
Page #
RDW Minor typo corrections
Various
RDW Added rise/fall variation to DC Electrical Characteristics Table
9
RDW Corrected Line 0 of NS_SAS Margining Table.
19
RDW Corrected MLF packaging pin description. Pin 37 was missing.
7
Updated Power Down Functionality table to clarify functionality of single-
RDW ended outputs in power down.
2
1. Added "Case Temperature" spec to Abs Max ratings
RDW 2. Added Thermal Characteristics
Various
1. Updated Phase Jitter Table to correct typo in "Conditions" column for
RDW SAS.
11, 23,
24
2. Mark Spec Added.
RDW ^{1. Updated Rp values on Output Terminations Table from 43.2 ohms to}
8
42.2 or 43.2 ohms to be consistent with Intel.
DC ^{1. Updated package drawing and dimensions from PUNCH to SAWN}
version.
Various
IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
27
932SQ420D
REV J 010715