ADC-318 Datasheet, PDF (1/8 Pages) List of Unclassifed Manufacturers – 8-Bit, 120MHz and 140MHz Full-Flash A/D Converter

®
®
ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz
Full-Flash A/D Converter
FEATURES
• Low power dissipation (960mW max.)
• TTL compatible output
• Diff./Integral nonlinearity (±½LSB max.)
• 1:2 Demultiplexed straight output programmable
• 2:1 Frequency divided TTL clock output with reset
• Surface mount package
• Selectable Input Logic (TTl, ECL, PECL)
• +5V or ±5V Power Supply Operation
GENERAL DESCRIPTION
The ADC-318 and ADC-318A are 8 bit monolithic bipolar,
full flash A/D converters. Though they have high, 120MHz
(ADC-318) and 140MHz (ADC-318A), sampling rates, their
input logic level, including the start convert pulse, is TTL,
ECL and PECL compatible. Digital outputs are also TTL
compatible and allow a straight output or a programmable
1:2 de-multiplexed output.
The ADC-318 and ADC-318A feature ±1/2 LSB max.
integral and differential non-linearity, +5V single or ±5V dual
power supply operation, a low 960mW maximum power
dissipation, 150MHz wide analog input range and excellent
temperature coefficient in a small 48 pin QFP package. The
start convert pulse can have a 50% duty cycle.
The ADC-318 and ADC-318A offer low cost, easy to use
functionality for design engineers.
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION
PIN FUNCTION
1
–DVs (Digital)
48
2
REF. BOTTOM (VRB)
47
3
ANALOG GROUND
46
4
REF. MID POINT (VRM1) 45
5
+AVS (Analog)
44
6
ANALOG IN (VIN)
43
7
REF. MID POINT (VRM2) 42
8
+AVS (Analog)
41
9
REF. MID POINT (VRM3) 40
10 ANALOG GROUND
39
11 REF. TOP (VRT)
38
12 DIGITAL GROUND 3
37
13 A/D CLOCK ECL/PECL 36
14 A/D CLOCK ECL/PECL 35
15 A/D CLOCK TTL
34
16 NO CONNECTION
33
17 NO CONNECTION
32
18 NO CONNECTION
31
19 +DVS2 (Digital)
30
20 DIGITAL GROUND 2
29
21 B BIT 8 (LSB)
28
22 B BIT 7
27
23 B BIT 6
26
24 B BIT 5
25
RSET ECL/PECL
RSET ECL/PECL
RSET TTL
SELECT
INV
TTL CLOCK OUT
+DVS2 (Digital)
DIGITAL GROUND 2
A BIT 1 (MSB)
A BIT 2
A BIT 3
A BIT 4
A BIT 5
A BIT 6
A BIT 7
A BIT 8 (LSB)
DIGITAL GROUND 2
+DVS2 (Digital)
+DVS1 (Digital)
DIGITAL GROUND 1
B BIT 1 (MSB)
B BIT 2
B BIT 3
B BIT 4
VIN 6
VRT 11
VRM3 9
VRM2 7
VRM1 4
VRB 2
A/D CLOCK ECL/PECL 13
A/D CLOCK ECL/PECL 14
A/D CLOCK TTL 15
RSET ECL/PECL 48
RSET ECL/PECL 47
RSET TTL 46
6
6
256
6
6
DELAY
D
Q
Q
8
A
LATCH
8
A
TTL
OUTPUT
44 INV
33 BIT 8 (LSB)
34 BIT 7
35 BIT 6
36 BIT 5 A OUTPUT
37 BIT 4
38 BIT 3
39 BIT 2
40 BIT 1 (MSB)
B
6
LATCH
B
TTL
OUTPUT
21 BIT 8 (LSB)
22 BIT 7
23 BIT 6
24 BIT 5 B OUTPUT
25 BIT 4
26 BIT 3
27 BIT 2
28 BIT 1 (MSB)
SELECT
43 CLOCK OUT
TTL
45 SELECT
Figure 1. ADC-318/318A Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: [phone] Fax: [phone] • Email: [e-mail] • Internet: www.datel.com