Z9952 Datasheet, PDF (2/9 Pages) Cypress Semiconductor – 3.3V, 180MHz, Multi-Output Zero Delay Buffer

Pin Description
PIN
NAME
6
REFCLK
12, 14, 15, QA(0:4)
18, 19
22, 23, 26, 27 QB(0:3)
30, 31
QC(0,1)
8
FB_IN
1
VCO_SEL
5
MR/OE#
9
2, 3, 4
PLL_EN#
SEL(C:A)
16, 20, 21,
25, 32
VDDC
10
VDDA
11
VDD
7, 13, 17, 24, VSS
28, 29
PD = Internal Pull-Down
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
PWR
VDDC
VDDC
VDDC
I/O
Description
I
External Test Clock Input.
O Clock Output. See Frequency Table.
O
O
I
I, PD
I, PD
I
I, PD
Clock Output. See Frequency Table.
Clock Outputs. See Frequency Table.
Feedback Clock Input. Connect to an output for normal operation.
VCO Divider Select Input. When set high, the VCO output is
divided by 2. When set low, the divider is bypassed. See
Table 1
Master Reset/Output Enable Input. When asserted high,
resets all of the internal flip-flops and also disables all of the
outputs. When pulled low, releases the internal flip-flops from
reset and enables all of the outputs.
PLL Enable Input. When asserted low, PLL is enabled. And
when set high, PLL is bypassed.
Frequency Select Inputs. See Frequency Table.
If SEL_ = 0, then QA, QB divider = ÷4, QC divider = ÷2
If SEL_ = 1, then QA divider = ÷6, QB divider = ÷2, QC divider
= ÷4
3.3V Power Supply for Output Clock Buffers.
3.3V Power Supply for PLL
3.3V Power Supply for Core Logic
Common Ground
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002
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