ZADCS1082 Datasheet, PDF (7/20 Pages) Zentrum Mikroelektronik Dresden AG – 10-Bit, 250ksps, Serial Output ADC Family

Datasheet
ZADCS1082/1042/1022 Family
1.5 Electrical Characteristics
1.5.1 General Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); VREF = 2.500V applied to VREF pin;
qOP = qOPmin … qOPmax)
Parameter
Symbol Conditions
Min Typ Max Unit
DC Accuracy
Resolution
10
Bits
Relative Accuracy
ZADCS1082 / ZADCS1082V
INL
ZADCS1042 / ZADCS1042V
ZADCS1022 / ZADCS1022V
± 0.4 LSB
No Missing Codes
NMC
10
Bits
Differential Nonlinearity
DNL
ZADCS1082 / ZADCS1082V
ZADCS1042 / ZADCS1042V
ZADCS1022 / ZADCS1022V
± 0.4 LSB
Offset Error
± 0.5 ± 2.0 LSB
Gain Error
± 0.5 ± 2.0 LSB
Gain Temperature Coefficient
± 0.25
ppm/°C
Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 250ksps, 3.3MHz external clock)
Signal-to-Noise + Distortion Ratio SINAD
Total Harmonic Distortion
THD
Up to the 5^th harmonic
61
dB
-72 dB
Spurious-Free Dynamic Range SFDR
74
dB
Small-Signal Bandwidth
-3dB roll off
3.8
MHz
Conversion Rate
Sampling Time
(= Track/Hold Acquisition Time)
tACQ
Ext. Clock = 3.3MHz, 2.5 clocks/ acquisi-
tion
0.758
µs
Conversion Time
tCONV
Ext. Clock = 3.3MHz, 10 clocks/ conver-
sion
Int. Clock = 3.3MHz +/- 12% tolerance 2.75
3.03 µs
3.50 µs
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
External Clock Frequency
0.1
3.3 MHz
Internal Clock Frequency
2.81 3.3 3.58 MHz
Analog Inputs
Input Voltage Range, Single-
Ended and Differential
Input Capacitance
Unipolar, COM = 0V
Bipolar, COM = VREF/2
0 to VREF
V
± VREF / 2
16
pF
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
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