ZADCS1282 Datasheet, PDF (19/21 Pages) Zentrum Mikroelektronik Dresden AG – 12-Bit, 200ksps, Serial Output ADC Family

Datasheet
ZADCS1282/1242/1222 Family
Figure 18: Average Supply Current versus Sampling
Rate
Current consumption vs. Sample Rate
External Clock Mode, External V_REF, f_SCLK = 3.2MHz
1000
100
10
1
1
10
100
1000
Sample Rate (ksps)
For optimal noise performance the star point should be
located very close to the AGND pin of the converter. The
ground return to the power supply should be as short as
possible and low impedance.
All other analog ground points of external circuitry that is
related to the A/D converter as well as the DGND pin of
the device should be connected to this ground point too.
Any other digital ground system should be kept apart as
far as possible and connect on the power supply point
only.
Analog and digital signal domains should also be sepa-
rated as well as possible and analog input signals should
be shielded by AGND ground planes from electromag-
netic interferences. Four-layer PCB boards that allow
smaller vertical distances between the ground plane and
the shielded signals do generally show a better perform-
ance than two-layer boards.
The sampling phase is the most critical portion of the
overall conversion timing for signal distortion. If possible,
the switching of any high power devices or nearby digital
logic should be avoided during the sampling phase of the
converter.
Figure 19: Optimal Power-Supply Grounding System
VDD
ZADCS12x2
Family
Optional
R = 10Ω
VDD1
(+2.7 … +5.25V)
AGND
COM
DGND
Other
DGND
Digital
Circuitry DVDD
GND
VDD2
The fully differential internal architecture of the
ZADCS12x2 family ensures very good suppression of
power supply noise. Nevertheless, the SAR architecture
is generally sensitive to glitches or sudden changes of the
power supply that occur shortly before the latching of the
comparator output. It is therefore recommended to by-
pass the power supply connection very close to the de-
vice with capacitors of 0.1µF (ceramic) and >1µF (electro-
lytic).
In case of a noisy supply, an additional series resistor of
5 to 10 ohms can be used to low-pass filter the supply
voltage.
The reference voltage should always be bypassed with
capacitors of 0.1µF (ceramic) and ≥ 4.7µF (electrolytic) as
close as possible to the VREF pin. If VREF is provided by
an external source, any series resistance in the VREF
supply path can cause a gain error of the converter. Dur-
ing conversion, a DC current of about 100µA is drawn
through the VREF pin that could cause a noticeable volt-
age drop across the resistance.
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
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