EZ80F915005MODG Datasheet, PDF (9/22 Pages) Zilog, Inc. – Real-time clock support

eZ80F91 Mini Enet Module
Product Specification
5
Note: All signals with an overline are active Low. For example, B/W, for
which WORD is active Low, and B/W, for which BYTE is active Low.
Table 1. eZ80Acclaim! Development Platform Peripheral Bus Connector J1 Identification^1,2
Pin No Symbol Signal Direction Active Level eZ80F91 Signal Comments
3
A6
Bidirectional
n/a
Yes
4
A0
Bidirectional
n/a
Yes
5
A7
Bidirectional
n/a
Yes
6
A2
Bidirectional
n/a
Yes
7
A8
Bidirectional
n/a
Yes
8
A1
Bidirectional
n/a
Yes
9
A102
Bidirectional
n/a
Yes
10
A3
Bidirectional
n/a
Yes
13
RD
Output
Low
Yes
14
D5
Bidirectional
n/a
Yes
15
D1
Bidirectional
n/a
Yes
16
D4
Bidirectional
n/a
Yes
17
D0
Bidirectional
n/a
Yes
18
D2
Bidirectional
n/a
Yes
19
A17
Bidirectional
n/a
Yes
20
D6
Bidirectional
n/a
Yes
23
A19
Bidirectional
n/a
Yes
24
A18
Bidirectional
n/a
Yes
25
A21
Bidirectional
n/a
Yes
26
A20
Bidirectional
n/a
Yes
Notes
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from this
table. The entire interface is represented in the eZ80F91 Mini Enet Module schematics on pages
16 through 17.
2. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should
be below 10 pF to satisfy the timing requirements for the eZ80 CPU. All unused inputs should be
pulled to either V_DD or GND, depending on their inactive levels to reduce power consumption and
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software
in the eZ80F91’s Peripheral Power-Down Register.
PS023603-0907
PRELIMINARY
Pin Description