Z89462 Datasheet, PDF (6/8 Pages) Zilog, Inc. – 16-BIT, FIXED-POINT DIGITAL SIGNAL PROCESSOR

PRELIMINARY
AC ELECTRICAL CHARACTERISTICS
(5.0V Operation)
Z89462
CP95DSP0400
Symbol
Parameter
Min.
TcCI
CLKIN Cycle Time
25
TwCIh
CLKIN Width High
10
TwCIl
CLKIN Width Low
10
TrCI
CLKIN Rise Time
TfCI
CLKIN Fall Time
TdCIr(Cr)
CLKIN Rise to CLK Rise Delay
TdCIf(Cf)
CLKIN Fall to CLK Fall Delay
TrC
CLK Rise Time
TfC
CLK Fall Time
TdCr(PA)
CLK Rise to PA Valid Delay
TdCr(PALSB) CLK Rise to PALSB Valid Delay
TdCr(PDSr)
CLK Rise to /PDS Rise Delay
TdCf(PDSf)
CLK Fall to /PDS Fall Delay
TsPW(Cr)
/PWAIT to CLK Rise Setup Time
5
ThPW(Cr)
/PWAIT to CLK Rise Hold Time
0
TsPSZ(Cr)
PDSZE to CLK Rise Setup Time
5
ThPSZ(Cr)
PDSZE to CLK Rise Hold Time
0
TdCr(PRDWR) CLK Rise to PRD//WR Delay
TsPD(Cr)
PD to CLK Rise Setup Time
5
ThPD(Cr)
PD to CLK Rise Hold Time
0
TdCR(PD)
CLK Rise to PD Valid Delay
TdCr(PDt)
CLK Rise to PD Tri-State Delay
TdCr(MA)
CLK Rise to MA Valid Delay
TdCr(MDSr)
CLK Rise to /MDS Rise Delay
TdCf(MDSf)
CLK Rise to /MDS Fall Delay
TsMW(Cr)
/MWAIT to CLK Rise Setup Time
5
ThMW(Cr)
/MWAIT to CLK Rise Hold Time
0
TdCr(MRDWR) CLK Rise to MRD//WR Delay
TsMD(Cr)
MD to CLK Rise Setup Time
5
ThMD(Cr)
MD to CLK Rise Hold Time
0
TdCr(MD)
CLK Rise to MD Valid Delay
TdCr(MDt)
CLK Rise to MD Tri-State Delay
TsINT(Cr)
INT2-0 to CLK Rise Setup Time
5
TwINTh
INT2-0 Width High
10
TwHLTHWl
/HLTHW Width Low
10
TwHLTHWh
/HLTHW Width High
2
TdCr(HLTOUT) CLK Rise to HLTOUT Delay
TwRESETl
/RESET Width Low
3
Notes:
[1] INT2-0 can also be asserted/deasserted asynchronously.
[2] These signals are asserted/deasserted asynchronously.
.
Max.
2
2
8
8
2
2
5
5
4
4
5
5
5
5
4
4
5
5
5
5
Unit
Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1]
ns
TcCI
[2]
TcCI
[2]
ns
TcCI
[2]
6