Z89303 Datasheet, PDF (5/8 Pages) Zilog, Inc. – DIGITAL TELEVISION CONTROLLER

PRELIMINARY
V1, V2, V3 ANALOG OUTPUT
Specifications V = 5.25 V
CC
V_CC = 5.25 V
Output Voltage
Settling Time
Condition
Bit = 11
Bit = 10
Bit = 01
Bit = 00
70% of DC Level, 10pf Load
Z89303/05/07
CPS DC-4222-03
Limit
4.55 V +/– 0.25 V
3.205V +/– 0.2 V
1.95 V +/– 0.15 V
0.65 V +/– 0.1 V
< 50 nsec
V1, V2, V3 ANALOG OUTPUT
Specifications V_CC = 4.75V
V_CC = 4.75V
Output Voltage
Settling Time
Condition
Bit = 11
Bit = 10
Bit = 01
Bit = 00
70% of DC Level, 10pf Load
Limit
3.90 V +/– 0.25 V
2.90 V +/– 0.2 V
1.90 V +/– 0.15 V
0.1 V +/– 0.1 V
< 50 nsec
Z893XX
32K Oscillator Recommended Circuit
Notes:
c) PWM[8,7] is not available on the 40-pin DIP version.
d) Port0[F:A] is not available on the 40-pin DIP version.
e) Port19 is not available on the 40-pin DIP version.
f) SCL I/O pin is shared with Port0 or Port11.
g) SCD I/O pin is shared with Port02 or Port12.
h) Half Blank output is a function shared with Port0F.
Half Blank output is not available on the 40-pin DIP version.
i) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
k) Internal processor SCLK is shared with Port16.
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