Z86L88 Datasheet, PDF (48/66 Pages) Zilog, Inc. – INFRARED REMOTE CONTROLLERS

Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
Port Configuration Register (PCON). The PCON regis-
ter configures the comparator output on Port 3. It is locat-
ed in the expanded register file at Bank F, location 00 (Fig-
ure 38).
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
Figure 38. Port Configuration Register (PCON)
(Write Only)
Comparator Output Port 3 (D0). Bit 0 controls the comparator
used in Port 3. A 1 in this location brings the comparator
outputs to P34 and P37, and a 0 releases the Port to its
standard I/O configuration.
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 39). All bits are write only ex-
cept bit 7, which is read only. Bit 7 is a flag bit that is hard-
ware set on the condition of STOP recovery and reset by
a power-on cycle. Bit 6 controls whether a low level or a
high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits D2, D3, and D4, or
the SMR register, specify the source of the Stop-Mode Re-
covery signal. Bits D0 determines determines if
SCLK/TCLK are divided by 16 or not. The SMR is located
in Bank F of the Expanded Register Group at address
0BH.
SMR (F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF **
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
0 11 P32
100 P33
101 P27
11 0 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery
* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery
Figure 39. Stop-Mode Recovery Register
OSC
÷2
÷ 16
SCLK
SMR, D0 ^TCLK
Figure 40. SCLK Circuit
48
PRELIMINARY
DS96LV00800