ZGP323H Datasheet, PDF (44/107 Pages) Zilog, Inc. – Programmable input glitch filter for pulse reception

ZGP323H
Product Specification
36
Table 16. CTR1(0D)01H T8 and T16 Common Functions (Continued)
Field
Transmit_Submode/
Glitch_Filter
Bit Position
----32--
Value
R/W
00*
01
10
11
Initial_T8_Out/
Rising Edge
------1-
00*
01
10
11
R/W 0*
1
Initial_T16_Out/
Falling_Edge
-------0
R
0*
1
W
0
1
R/W 0*
1
R
0*
1
W
0
1
Note:
*Default at Power-On Reset
*Default at Power-On Reset. Not reset with Stop Mode recovery.
Description
Transmit Mode
Normal Operation
Ping-Pong Mode
T16_Out = 0
T16_Out = 1
Demodulation Mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
Reserved
Transmit Mode
T8_OUT is 0 Initially
T8_OUT is 1 Initially
Demodulation Mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0
Transmit Mode
T16_OUT is 0 Initially
T16_OUT is 1 Initially
Demodulation Mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0
Mode
If the result is 0, the counter/timers are in TRANSMIT mode; otherwise, they are in
DEMODULATION mode.
P36_Out/Demodulator_Input
In TRANSMIT Mode, this bit defines whether P36 is used as a normal output pin
or the combined output of T8 and T16.
In DEMODULATION Mode, this bit defines whether the input signal to the
Counter/Timers is from P20 or P31.
If the input signal is from Port 31, a capture event may also generate an IRQ2
interrupt. To prevent generating an IRQ2, either disable the IRQ2 interrupt by
clearing its IMR bit D2 or use P20 as the input.
PS023803-0305
Functional Description