Z86L78 Datasheet, PDF (43/59 Pages) Zilog, Inc. – IR/Low-Voltage Microcontroller

Zilog
Z86L78
IR/Low-Voltage Microcontroller
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR Note: Any Port 2 bit defined as an output will drive the cor-
controls a Divide-by-16 prescaler of SCLK/TCLK (Figure responding input to the default state to allow the remaining
1 ^{34). The purpose of this control is to selectively reduce de- inputs to control the AND/OR function. Refer to SMR2 reg-}
vice power consumption during normal processor execu- ister for other recover sources.
tion (SCLK control) and/or HALT Mode (where TCLK
sources interrupt logic). After Stop-Mode Recovery, this bit ^{STOP-Mode Recovery Delay Select (D5). This bit, if}
is set to a 0.
Low, disables the 5 ms /RESET delay after Stop-Mode Re-
covery. The default configuration of this bit is one. If the
"fast" wake up is selected, the Stop-Mode Recovery
source needs to be kept active for at least 5TpC.
OSC
÷2
STOP-Mode Recovery Edge Select (D6). A 1 in this bit
position indicates that a High level on any one of the recov-
ery sources wakes the Z86L78 from STOP Mode. A 0 in-
dicates Low level recovery. The default is 0 on POR (Fig-
ure 35).
÷ 16
SCLK
SMR, D0 ^TCLK
Figure 34. SCLK Circuit
STOP-Mode Recovery Source (D2, D3, and D4). These
three bits of the SMR specify the wake up source of the
STOP recovery (Figure 35 and Table 5).
Table 5. STOP-Mode Recovery Source
SMR: 432
D4
D3
D2
Operation
Description of Action
0
0
0 POR and/or external reset
recovery
0
0
1 Reserved
0
1
0 P31 transition
0
1
1 P32 transition
1
0
0 P33 transition
1
0
1 P27 transition
1
1
0 Logical NOR of P20 through
P23
1
1
1 Logical NOR of P20 through
P27
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. It is a Read Only Flag bit. A 1
in D7 (warm) indicates that the device will awaken from a
SMR source or a WDT while in STOP Mode. A 0 in this bit
(cold) indicates that the device will be rest by a POR, WDT
while not in STOP, or the device awakened from a low volt-
age standby mode.
Stop-Mode Recovery Register 2 (SMR2). This register
determines the mode of stop mode recovery for SMR2
(Figure 36).
If SMR2 is used in conjunction with SMR, either of the
specified events will cause a Stop-Mode Recovery.
Note: Port pins configured as outputs are ignored as a
SMR or SMR2 recovery source. For example, if the NAND
of P23-20 is selected as the recovery source and P20 is
configured as an output then the remaining SMR pins
(P23-P21) form the NAND equation.
DS97LVO0701
2-43