Z89331 Datasheet, PDF (4/7 Pages) Zilog, Inc. – OTP DIGITAL TELEVISIONCONTROLLER

PIN DESCRIPTIONS
Z89331
PRELIMINARY
Pin
Name
V
CC
GND
IRIN
ADC[5:0]^a
PWM9
Function
+5 V
0V
Infrared Remote Capture Input
4-Bit Analog to Digital Converter
Input^b
14-Bit Pulse Width Modulator
Output
Z89331
42-Pin SDIP
34
13,30
36
–,9,10,11,12,2,8
1,2
Z89331
CP95TEL1400
Configuration
Direction Reset
PWR PWR
PWR
I
AI
PWR
I
I
OD
O
PWM[8:1]^c
Port0[F:0]^d
8-Bit Pulse Width Modulator
Output
Bit Programmable
Input/Output Ports
Port1[9:0]^e Bit Programmable
Input/Output Ports
MSSCL^f
MSSCD^g
SSCL^h
SSCDⁱ
XTAL1
XTAL2
LPF
I²C Clock I/O
I²C Data I/O
I²C Clock I/O
I²C Data I/O
Crystal Oscillator Input
Crystal Oscillator Output
Loop Filter
–,–,–,3,4
5,6,7
21,–,–,–,–,–,
38,37,35,–,–,
15,8,40,39,11
–,16,12,20,
19,18,17,42,
41,14
41
42
39
40
31
32
29
OD
OD
B
I
B
I
BOD
BOD
I
BOD
I
BOD
I
AI
AI
AO
AO
AB
AB
HSYNC
VSYNC
H_Sync
V_Sync
26
B
I
27
B
I
/RESET
Device Reset
V[3:1]
Blank
Half Blank^h
OSD Video Output
(Typically Drive B, G, and R Outputs)
OSD Blank Output
OSD Half Blank Output
RGB Digital R[1:0],G[1:0], and B[1:0]
Outputsⁱ
Outputs of the RGB Matrix
SCLK^k
Internal Processor SCLK
33
22,23,24
25
21
37,14,17,
16,19,18
20
I
I
O
O
O
O
O
I
O
I
O
I
Notes:
a) ADC1 input is shared with Port 17, ADC2 input Pin is shared with
Port 00. ADC3 input pin is shared with Port 05 and ADC4 input pin
is shared with Port 04.
b) ADC0 and ADC5 have a clamp circuit that facilitates Composite
video input.
c) PWM[8,7] is not available on the 42-pin DIP version.
d) Port0[F:A] is not available on the 42-pin DIP version.
e) Port19 is not available on the 42-pin DIP version.
f) SCL I/O pin is shared with Port01 or Port11.
g) SCD I/O pin is shared with Port02 or Port12.
h) Half Blank output is a function shared with Port0F.
i) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
k) Internal processor SCLK is shared with Port16.
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