Z89302 Datasheet, PDF (4/8 Pages) Zilog, Inc. – Digital Television Controller

Z89302/04/06
Digital Television Controller
PIN DESCRIPTIONS
Z89302/03/06/07
PRELIMINARY
Pin Name Function
40-Pin, Z89302/04/06
Reset
Direction Configuration
V_CC
+5V
GND
0V
29,–
PWR–
31,–
PWR–
IRIN
Infrared Remote Capture Input
2
I
I
ADC[5:0]
4-Bit Analog to Digital
Converter Input
–,9,8,4,27,34
nAI
I
PWM9
14-Bit Pulse Width Modulator
1
Output
OD/O^a
O
PWM[8:1]
8-Bit Pulse Width Modulator
Output
–,–,40,39,38
OD/O^a
O
Port0[F:0] Bit Programmable Input/Output –,–,–,–,–,–,13,12,11,10,9,8,7,6,5,4
B
I
Ports
Port1[9:0] Bit Programmable Input/Output
–,3,27,20,19,18,17,16,15,14
B
I
Ports
SCL^b
I²C Clock I/O
5 or 15
BOD
SCD^c
I²C Data I/O
6 or 16
BOD
XTAL1
Crystal Oscillator Input
30
AI
I
XTAL2
Crystam Oscillator Output
32
AO
O
LPF
Loop Filter
33
AB
O
HSYNC
H_Sync
21
B
I
VSYNC
V_Sync
22
B
I
/RESET
Device Reset
28
I
I
V[3:1]
OSD Video Output (Typically
Drive B, G, and R Outputs)
23,24,25
O
O
Blank
OSD Blank Output
26
O
O
Half Blank^d
RGB Digital
Outputs^e
OSD Half Blank Output
R[1:0],G[1:0], and B[1:0]
Outputs of the RGB Matrix
–
19,18,17,14,12,3
O
I
O
SCLK^f
Internal Processor SCLK
O
Notes:
a) Port19 is not available on the 40-pin DIP Version, Revision D is Push-Pull.
b) SCL I/O pin is shared with Port01 or Port11
c) SCD I/O pin is shared with Port02 or Port12
d) Half Blank output is a function shared with Port0F. Half Blank output is not available on the 40-pin DIP version.
e) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
f) Internal processor SCLK is shared with Port16.
4