ZLR32300 Datasheet, PDF (30/98 Pages) Zilog, Inc. – Z8 Low-Voltage ROM MCU with Infrared Timers

Crimzon^TM ZLR32300
Product Specification
22
Comparator Inputs
In analog mode, P31 and P32 have a comparator front end. The comparator refer-
ence is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its
corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and
P33) as indicated in Figure 11 on page 19. In digital mode, P33 is used as D3 of
the Port 3 input register, which then generates IRQ1.
Note: Comparators are powered down by entering STOP mode. For
P31–P33 to be used in a STOP mode Recovery source, these
inputs must be placed into digital mode.
Comparator Outputs
These channels can be programmed to be output on P34 and P37 through the
PCON register.
RESET (Input, Active Low)
Reset initializes the MCU and is accomplished either through Power-On, Watch-
Dog Timer, STOP mode Recovery, Low-Voltage detection, or external reset. Dur-
ing Power-On Reset and Watch-Dog Timer Reset, the internally generated reset
drives the reset pin Low for the POR time. Any devices driving the external reset
line must be open-drain to avoid damage from a possible conflict during reset con-
ditions. Pull-up is provided internally.
When the ZLR32300 asserts (Low) the RESET pin, the internal pull-up is dis-
abled. The ZLR32300 does not assert the RESET pin when under VBO.
Note: The external Reset does not initiate an exit from STOP mode.
Functional Description
This device incorporates special functions to enhance the Z8^®’ functionality in
consumer and battery-operated applications.
Program Memory
This device addresses 32KB of ROM memory. The first 12 Bytes are reserved for
interrupt vectors. These locations contain the six 16-bit vectors that correspond to
the six available interrupts. See Figure 13.
RAM
This device features 256B of RAM.
PS022607-1205
Functional Description