English
Language : 

Z86228 Datasheet, PDF (3/7 Pages) Zilog, Inc. – LINE 21 CLOSED CAPTION CONTROLLER (L21C)
Horizontal Timing
PRELIMINARY
Z86228
CPS DC-4243-00
The timing of the output signals; Box, Luminance, and RGB
is set so that the start of the leading box preceding the first
displayable character cell will occur at 13.6*µs. (*Value
may be altered by a Mask change - consult factory.) This
is after the midpoint of the leading edge of the horizontal
sync pulse of the composite video signal measured at pin
11 of the Z86228. It is assumed that the delay through the
low pass filter will be 220 ns (refererence Figure).
There are two ways to execute a FULL RESET of the
Z86228:
1. Hold NRESET Low for 100 ns. This stops all internal
circuits. The part is static and the 100 ns is the worst
case time for the NRESET signal to propagate through
the various gates.
2. Send NRESET command through the serial interface.
The result is the same as in number 1.
FULL RESET is useful during power-up. A FULL RESET of
the part during normal operation is not necessary.
A partial reset may also be executed through the serial
interface only. This is the COMMAND PROCESSOR RESET.
Basically, all internal timing circuits continue to operate,
but the caption display is removed from the screen and the
Z86228 waits for new line 21 data. This is useful for
situations such as channel change.
ABSOLUTE MAXIMUM RATINGS
Sym Description
Min Max Units
Vcc
Supply Voltage*
–0.3 +7.0 V
TSTG Storage Temp
–65°C +150° C
T
A
Oper Ambient Temp
0° 70° C
Notes:
* Voltages on all pins with respect to GND.
Stress greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for an extended period may
affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin in Standard
Test Load.
From Output
Under Test
150 pF
+5V
2.1 kΩ
w 250 µA
Standard Test Load
3