ZGP323L Datasheet, PDF (27/105 Pages) Zilog, Inc. – Programmable input glitch filter for pulse reception

Z8 GP^TM OTP MCU Family
Product Specification
21
CTR1(0D)01H” on page 33). Other edge detect and IRQ modes are described in
Table 11.
Note: Comparators are powered down by entering Stop Mode. For
P31–P33 to be used in a Stop Mode Recovery (SMR) source,
these inputs must be placed into digital mode.
2
Table 11. Port 3 Pin Function Summary
Pin
I/O
Pref1/P30 IN
P31
IN
P32
IN
P33
IN
P34
OUT
P35
OUT
P36
OUT
P37
OUT
P20
I/O
Counter/Timers Comparator Interrupt
RF1
IN
AN1
IRQ2
AN2
IRQ0
RF2
IRQ1
T8
AO1
T16
T8/16
AO2
IN
Port 3 also provides output for each of the counter/timers and the AND/OR Logic
(see Figure 13). Control is performed by programming bits D5–D4 of CTR1, bit 0
of CTR0, and bit 0 of CTR2.
PS023702-1004
Preliminary
Pin Functions